Joint Test Action Group (JTAG) is the common name for what was later standardized as the IEEE 1149.1 Standard Test Access Port and Boundary-Scan Architecture. It was originally designed for testing printed circuit boards using boundary scan, but JTAG testing has expanded to integrated circuits (e.g., processors, controllers, etc.), embedded systems, and other components. JTAG is also used for performing debug testing of sub-blocks of integrated circuits.
Generally, JTAG testing is implemented via facilities that are built into the device being tested (commonly referred to as the Device under Test or DUT) and an external tester that connects to the DUT via a debug or test port and provides stimulus and control signals to the DUT to implement various tests such as scan tests and logic debug tests and receives test result signals and data output from the DUT. This test result data and signals can then be processed to verify the operation of the DUT. Typically, devices such as processors or Systems on a Chip (SoCs) have pins that are electronically connected to the JTAG tester via a debug port coupled to a socket the processor is mounted in. Similar debug ports may be provided at the board level, although there are instances where JTAG is used only for design debug and the production boards do not include a debug port and/or debug port connector or other type of JTAG interface.
For example, oftentimes if a debug port connector is implemented in a target system, the platform components are depopulated for production product versions. When these platforms require JTAG and run-control to diagnose potential silicon/platform/driver/software issues, it is often not possible to rework the debug port connector into the system due to rework restrictions on final product, or the potential for issues to not reproduce after the system is instrumented (often involving a full disassembly, rework, and reassembly). Moreover, debug ports and their connectors are very application specific and not configured to support standard communication. Thus, inclusion of debug ports and connectors on production devices incurs additional part and assembly cost.
In view of the foregoing, it would be advantageous to perform device testing such as JTAG testing on production devices and systems as fully assembled and enclosed in their standard chassis (e.g., laptops, notebooks, desktops, servers, or handheld devices), without requiring conventional test interfaces or debug ports, and preferably without augmenting the packaging of such devices and systems.